Device for amplitude adjustment and rectification made with MOS technology

ABSTRACT

An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics. A full-wave rectifier, applicable to the amplitude adjustment device, is mainly configured by an inversion amplifier, an amplifier and an output section. Herein, the inversion amplifier amplifies an input signal with a gain of “−1”, while the amplifier amplifies it with a gain of “1”. Outputs of the amplifiers differ from each other in phases by 180°. The output section produces a full-wave rectified signal based on the outputs of the amplifiers. Incidentally, all of the amplifiers and output section are configured using field-effect transistors without using diodes being externally connected. Hence, it is possible to manufacture the full-wave rectifier in a form of an IC in accordance with the MOS process with ease.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to amplitude adjustment devices such asamplitude compression devices and amplitude expansion devices, which aremade with the MOS (i.e., Metal-Oxide Semiconductor) technology. Inaddition, this invention also relates to full-wave rectifiers,applicable to the amplitude adjustment devices, which are made with theMOS technology. Specifically, the devices are used for amplitudeadjustment and rectification of audio inputs of digital audio systems.

[0003] This application is based on Patent Application No. Hei 10-180864and Patent Application No. Hei 10-180865 both filed in Japan, thecontents of which are incorporated herein by reference.

[0004] 2. Description of the Related Art

[0005] Conventionally, amplitude compression/expansion devices are usedfor compressing and expanding signals of audio playback systems or audioreproduction systems. In the case of the automobiles, for example,drivers normally hear the noise due to the running of the automobileswhen listening to the music which is played back with audio devices. So,if the drivers play back the music having a broad dynamic range such asthe classic music, the drivers are hard to listen to piano sounds whichare performed in pianissimo, for example. To improve such hardness inlistening to the music in the automobiles, amplitude compression devicescalled “compressors” are used for the audio devices so that musical tonesignals having small amplitudes are reproduced with a relatively largegain while musical tone signals having large amplitudes are reproducedwith a relatively small gain.

[0006] There are provided three examples as the aforementioned amplitudecompression devices, as follows:

[0007]FIG. 11 shows a circuit configuration for a first example of theamplitude compression device, which uses a voltage control amplifier.Herein, the voltage control amplifier 100 contains a multiplier, whichis configured using bipolar transistors. The voltage control amplifier100 adjusts an amplitude of an input signal Vin based on a controlsignal Cs. Thus, the voltage control amplifier 100 produces an outputsignal Vout in response to the input signal Vin. An amplitude detectioncircuit 110 is configured by a full-wave rectifier and a low-passfilter. The amplitude detection circuit 110 produces the control signalCs in response to an amplitude of the output signal Vout. Normally, thebipolar transistors have base-emitter voltage characteristics, whichshow logarithmic characteristics. Using such characteristics, thevoltage control amplifier 100 adjusts the amplitude of the input signalVin.

[0008]FIG. 12 shows a circuit configuration for a second example of theamplitude compression device, which uses a gain switching amplifier.Herein, the gain switching amplifier 200 has a capability of switchingover gains thereof based on control data Dc. In addition, an amplitudedetection circuit 210 detects an amplitude of an output signal Vout. So,the amplitude detection circuit 210 produces the control data Dc inresponse to the detected amplitude. Incidentally, the gain switchingamplifier 200 has a number of steps in changing the gains, which arecalled “gain steps”. Herein, the number of gain steps corresponds to anumber of bits of the control data Dc.

[0009]FIG. 13 shows a circuit configuration for a third example of theamplitude compression device, which uses a digital signal processor(i.e., DSP). Herein, an input signal Vin is supplied to a DSP 310 via ananalog-to-digital converter (or A/D converter). The DSP 310 detects anamplitude of the input signal Vin. Then, the DSP 310 performs non-linearamplification based on the detected amplitude, thus producing outputdata thereof. A digital-to-analog converter 320 (or D/A converter)converts the output data of the DSP 310 to an analog signal, which isoutput as an output signal Vout.

[0010] The aforementioned examples of the amplitude compression devicessuffer from problems, as follows:

[0011] The first example of the amplitude compression device shown inFIG. 11 is designed such that the voltage control amplifier 100 isconfigured using the bipolar transistors, wherein amplitude compressionis performed using the logarithmic characteristics of the bipolartransistors. So, it is impossible to manufacture the amplitudecompression device in a form of an IC in accordance with the MOS process(or MOS technology). For this reason, the first example of the amplitudecompression device suffers from a problem in which it has a limitedrange of application.

[0012] In the second example of the amplitude compression device, thegain switching amplifier 200 cannot change the gains thereof in acontinuous manner. Therefore, the output signal should be madediscontinuous in response to gain switching timings. Thus, the secondexample suffers from a problem in which it cannot produce the outputsignal which is “smooth”.

[0013] The third example of the amplitude compression device uses theDSP 310, which requires conversion from analog signals to digitalsignals and conversion from digital signals to analog signals. For thisreason, the third example suffers from a problem in which it has acomplicated circuit configuration.

[0014] By the way, full-wave rectifiers are known as devices thatperform full-wave rectification on signal voltages to detect amplitudevalues of signals. FIG. 14 shows an example of a circuit configurationfor the full-wave rectifier. The full-wave rectifier of FIG. 14 ismainly configured by a half-wave rectifier and an addition circuit of aninversion type. Herein, the half-wave rectifier is configured byresistors 110, 120, diodes D1, D2 and an operational amplifier OP1,while the addition circuit is configured by resistors 130, 140, 150 andan operational amplifier OP2. All of the resistors 110 to 140 have sameresistance “R”, while the resistor 150 has resistance of “R/2”.

[0015] The half-wave rectifier is configured such that the diodes D1, D2cancel voltage drops Vf in forward directions. Therefore, a half-waverectified signal V′ increases in a positive direction from a groundlevel. For example, if an input signal Vin shown in FIG. 15A is appliedto the half-wave rectifier, its half-wave rectified signal V′ is shownin FIG. 15B.

[0016] In the addition circuit of the inversion type which is configuredby the resistors 130 to 150 having the aforementioned resistancesrespectively, it is possible to perform addition on the input signal Vinwith a gain “−1”, while it is possible to perform addition on thehalf-wave rectified signal V′ with a gain “−2”. Therefore, an outputsignal Vout of the addition circuit is shown in FIG. 15C.

[0017] As described above, the full-wave rectifier is configured usingtwo diodes and two operational amplifiers (OP1, OP2), wherein thehalf-wave rectified signal V′ is produced and is mixed with the inputsignal Vin so that the output signal Vout is created.

[0018] The aforementioned full-wave rectifier can be applied to an audiosignal processing circuit in order to detect amplitudes of reproducedaudio signals, wherein processing is performed in response to theamplitudes of the reproduced audio signals. Engineers wish tomanufacture such audio signal processing circuit in a form of a LSIcircuit in accordance with the CMOS process (where “CMOS” is anabbreviation for “Complementary Metal-Oxide Semiconductor”). However, itis impossible to form the diodes by the CMOS process. So, there is adisadvantage in that the diodes should be provided as externalcomponents which are attached to the LSI circuit.

SUMMARY OF THE INVENTION

[0019] It is an object of the invention to provide an amplitudecompression device and an amplitude expansion device, which have simplecircuit configurations and which can be manufactured as ICs inaccordance with the MOS process with ease.

[0020] It is another object of the invention to provide the amplitudecompression device and amplitude expansion device, in which gains can bevaried continuously.

[0021] It is a further object of the invention to provide a full-waverectifier, which is configured using field-effect transistors withoutusing diodes being externally connected.

[0022] In one aspect of the invention, there is provided an amplitudeadjustment device such as an amplitude compression device and amplitudeexpansion device, which is basically configured by a PWM modulator, ademodulator and an amplitude detector. Herein, the PWM modulator effectspulse-width modulation on an input signal to produce a pulse-widthmodulated signal, which is demodulated by the demodulator to produce anoutput signal (and a demodulated signal). In addition, the amplitudedetector detects an amplitude of the demodulated signal or an amplitudeof the input signal to produce a control signal. A modulation factor ofthe pulse-width modulation is adjusted based on the control signal.Herein, the control signal controls a feedback value, which correspondsto a fraction of the pulse-width modulated signal and which is fed backthrough a negative feedback loop in the PWM modulator. In the case ofthe amplitude compression device, for example, an input/output gain ischanged inversely proportional to the amplitude of the input signal oramplitude of the output signal. That is, the input/output gain isincreased as the amplitude of the input signal (or output signal)decreases, while the input/output gain is decreased as the amplitude ofthe input signal (or output signal) increases. Thus, it is possible tocompress a dynamic range with respect to input/output characteristics.

[0023] In another aspect of the invention, there is provided a full-waverectifier, applicable to the amplitude adjustment device, which ismainly configured by an inversion amplifier, an amplifier and an outputsection. Herein, the inversion amplifier amplifies an input signal witha gain of“−1”, while the amplifier amplifies it with a gain of “1”.Outputs of the amplifiers differ from each other in phases by 180°. Theoutput section produces a full-wave rectified signal based on theoutputs of the amplifiers. Specifically, the output section selectseither the output signal of the inversion amplifier or the output signalof the amplifier in response to every half of one period of the inputsignal. For example, the output signal of the inversion amplifier isselected and is used for formation of a first portion of a full-waverectified signal in a first half duration of one period of the inputsignal. In addition, the output signal of the amplifier is selected andis used for formation of a second portion of the full-wave rectifiedsignal in a second half duration. The first and second portions arecombined together to form a “negative” waveform for the full-waverectified signal in response to one period of the input signal.Incidentally, all of the amplifiers and output section are configuredusing field-effect transistors without using diodes being externallyconnected. Hence, it is possible to manufacture the full-wave rectifierin a form of an IC in accordance with the MOS process with ease.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] These and other objects, aspects and embodiments of the presentinvention will be described in more detail with reference to thefollowing drawing figures, of which:

[0025]FIG. 1 is a block diagram showing an amplitude compression devicein accordance with embodiment 1 of the invention;

[0026]FIG. 2 is a circuit diagram showing a circuit configuration of theamplitude compression device of FIG. 1;

[0027]FIG. 3A shows a waveform of an input signal Vin applied to a PWMmodulator shown in FIG. 2;

[0028]FIG. 3B shows a pulse-width modulated signal Vm, which is producedby the PWM modulator;

[0029]FIG. 3C shows the pulse-width modulated signal, which is given byadjusting a feedback value in the PWM modulator;

[0030]FIG. 3D shows a waveform of a demodulated signal V′, which isdemodulated from the pulse-width modulated signal;

[0031]FIG. 4 is a graph showing an example of input/outputcharacteristics of the amplitude compression device of FIG. 2;

[0032]FIG. 5 is a block diagram showing a configuration of an amplitudecompression device in accordance with embodiment 2 of the invention;

[0033]FIG. 6 is a circuit diagram showing a circuit configuration of theamplitude compression device of FIG. 5;

[0034]FIG. 7 is a circuit diagram showing a circuit configuration of afull-wave rectifier in accordance with embodiment 3 of the invention;

[0035]FIG. 8A shows a waveform of an input signal Vin applied to thefull-wave rectifier of FIG. 7;

[0036]FIG. 8B shows a waveform of gate voltage VG1 in FIG. 7;

[0037]FIG. 8C shows a waveform of gate voltage VG2 in FIG. 7;

[0038]FIG. 8D shows a waveform of an output signal Vout in FIG. 7;

[0039]FIG. 9 is a circuit diagram showing a circuit configuration of afull-wave rectifier in accordance with embodiment 4 of the invention;

[0040]FIG. 10A shows a waveform of an input signal Vin applied to thefull-wave rectifier of FIG. 9;

[0041]FIG. 10B shows a waveform of gate voltage VG11 in FIG. 9;

[0042]FIG. 10C shows a waveform of gate voltage VG12 in FIG. 9;

[0043]FIG. 10D shows a waveform of an output signal Vout in FIG. 9;

[0044]FIG. 11 is a block diagram showing a first example of theamplitude compression device;

[0045]FIG. 12 is a block diagram showing a second example of theamplitude compression device;

[0046]FIG. 13 is a block diagram showing a third example of theamplitude compression device;

[0047]FIG. 14 is a circuit diagram showing an example of a circuitconfiguration for a full-wave rectifier;

[0048]FIG. 15A shows a waveform of an input signal Vin applied to thefull-wave rectifier of FIG. 14;

[0049]FIG. 15B shows a waveform of a half-wave rectified signal V′,which is produced by a half-wave rectifier contained in the full-waverectifier of FIG. 14; and

[0050]FIG. 15C shows a waveform of an output signal Vout, which isoutput from the full-wave rectifier of FIG. 14.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0051] This invention will be described in further detail by way ofexamples with reference to the accompanying drawings.

[0052] [A] Embodiment 1

[0053] Now, a description will be given with respect to a circuitconfiguration of an amplitude compression device in accordance withembodiment 1 of the invention. FIG. 1 is a block diagram showing theamplitude compression device of the embodiment 1. The amplitudecompression device of FIG. 1 contains a PWM modulator 10 (where “PWM” isan abbreviation for “Pulse-Width Modulation”), a main part of which isconfigured by a self-sustaining oscillation circuit. Herein, the PWMmodulator 10 performs pulse-width modulation on an input signal Vin inresponse to a modulation factor, which is determined by a control signalCs. Thus, the PWM modulator 10 produces and outputs a pulse-widthmodulated signal Vm.

[0054] A demodulator 20 is configured using a low-pass filter. Thedemodulator 20 demodulates the pulse-width modulated signal Vm toproduce an output signal Vout. The low-pass filter has “flat” frequencycharacteristics in a frequency band of the input signal Vin. Inaddition, the low-pass filter has “sufficient” attenuationcharacteristics in frequency ranges in proximity to a carrier frequencyof the pulse-width modulated signal Vm.

[0055] An amplitude detector 30 detects an amplitude of the outputsignal Vout. Thus, the amplitude detector 30 produces the control signalCs in response to the detected amplitude.

[0056] Next, details of the amplitude compression device of FIG. 1 willbe described with reference to FIG. 2, which shows internal circuitconfigurations of the circuit blocks 10, 20 and 30.

[0057] The PWM modulator 10 is configured by an operational amplifier11, buffers 12 to 14, resistors R1 to R5 and capacitors C1, C2. Herein,two source voltages, i.e., positive source voltage vh and negativesource voltage vl, are applied to the buffer 13, wherein those voltagescan be adjusted. In addition, the buffer 14 is equipped with a positiveoutput terminal and a negative output terminal.

[0058] In the PWM modulator 10 shown in FIG. 2, the resistor R4 isinserted between an output terminal of the buffer 12 and a noninvertinginput of the operational amplifier 11. So, an output of the buffer 12 issubjected to voltage division by the resistors R4 and R3. Thus, afractional output, which is divided, is fed back to the noninvertinginput of the operational amplifier 11. A high-pass filter configured bythe capacitors C1, C2 and the resistor R5 is provided between aninverting input and an output terminal of the operational amplifier 11.Therefore, high-frequency components of an output of the operationalamplifier 11 are fed back to the inverting input of the operationalamplifier 11. The aforementioned circuit components are assembledtogether to form an oscillation circuit. Herein, the output of theoperational amplifier 11 is an equivalence of a result of quadraticintegration which is performed on the input signal Vin and an output ofthe buffer 13. In addition, an output of the buffer 12 which receivesthe output of the operational amplifier 11 is a two-valued signal, whichis given as source voltage or ground voltage.

[0059] The input signal Vin is supplied to the inverting input of theoperational amplifier 11 via the resistor R1. In addition, the output ofthe buffer 13 is fed back to the inverting input of the operationalamplifier 11 via the resistor R2. The aforementioned source voltages vh,vl applied to the buffer 13 are adjusted in response to detectionresults of the amplitude detector 30. The output of the buffer 13 is atwo-valued signal having a high level and a low level, which correspondto the voltages vh and vl respectively. Therefore, it is possible toadjust a feedback ratio (or feedback factor) for the pulse-widthmodulated signal Vm, which is fed back to the PWM modulator 10 via theamplitude detector 30, in response to the voltages vh, vl. If thevoltages vh, vl are reduced, a feedback value is reduced as well. Incontrast, if the voltages vh, vl are increased, the feedback value isincreased. Therefore, the feedback value is adjusted in response to anamplitude of the output signal Vout.

[0060] In the PWM modulator 10, a duty ratio for the output of thebuffer 12 is varied in response to a voltage value of the input signalVin so that the pulse-width modulation is effected. Herein, themodulation factor is varied in response to the feedback value of theoperational amplifier 11. That is, the modulation factor increases ifthe feedback value decreases, while the modulation factor decreases ifthe feedback value increases.

[0061] The demodulator 20 is equipped with a first low-pass filter and asecond low-pass filter. That is, the first low-pass filter is configuredby resistors R8, R9 and capacitors C8, C9, while the second low-passfilter is configured by resistors R6, R7 and a capacitor C7. Herein, thefirst low-pass filter is connected to the positive output terminal ofthe buffer 14. So, the first low-pass filter demodulates the pulse-widthmodulated signal Vm to produce an output signal Vout. The secondlow-pass filter is connected to the negative output terminal of thebuffer 14. So, the second low-pass filter demodulates an inverse (orinverted signal) Vm′ of the pulse-width modulated signal Vm to produceand output a demodulated signal V′. Incidentally, the demodulator 20 canbe modified such that the first low-pass filter is connected to thenegative output terminal of the buffer 14 while the second low-passfilter is connected to the positive output terminal of the buffer 14. Insuch modification, it is possible to match an input phase with an outputphase.

[0062] The first and second low-pass filters have frequencycharacteristics, which have “sufficient” attenuation characteristics infrequency ranges in proximity to the carrier frequency of thepulse-width modulated signal Vm. Thus, it is possible to sufficientlyremove carrier frequency components, so it is possible to improve a S/Nradio for the output signal Vout. In the demodulator 20, the firstlow-pass filter is configured in a form of second order, while thesecond low-pass filter is configured in a form of first order. Reasonsare as follows:

[0063] The first low-pass filter is provided to obtain the output signalVout, so it requires the sufficient attenuation characteristics. Incontrast to the first low-pass filter, the second low-pass filter isprovided for control. So, the second low-pass filter does not requirethe strict specification, which is required for the first low-passfilter.

[0064] An output of the second low-pass filter is connected to a cathodeof a diode D1 and an anode of a diode D2, which are provided within theamplitude detector 30. In the amplitude detector 30, an anode of thediode D1 is connected to a capacitor C6, while a cathode of the diode D2is connected to a capacitor C7. Herein, the diode D1 and the capacitorC6 configure a hold circuit which holds a negative peak voltage value ofthe demodulated signal V′. In addition, the diode D2 and the capacitorC5 configure another hold circuit which holds a positive peak voltagevalue of the demodulated signal V′.

[0065] In the amplitude detector 30, a subtraction circuit is configuredby an operational amplifier 31 and resistors R10 to R13. The subtractioncircuit subtracts the negative peak voltage value from the positive peakvoltage value so as to calculate an amplitude value of the demodulatedsignal V′. In addition, an inverter circuit is configured by anoperational amplifier 32 and resistors R14, R15. The inverter circuitinverts an output of the operational amplifier 31. Therefore, outputs ofthe operational amplifiers 31, 32 represent a detection result of theamplitude value of the demodulated signal V′. Those outputs are suppliedto the PWM modulator 10 as the control signal Cs. Incidentally, thedemodulated signal V′ is produced by demodulating the inverted signalVm′ of the pulse-width modulated signal Vm. As a result, the amplitudedetector 30 is capable of detecting the amplitude of the output signalVout.

[0066] Next, a description will be given with respect to operations ofthe amplitude compression device with reference to time charts of FIGS.3A, 3B, 3C and 3D. An input signal Vin shown in FIG. 3A is applied tothe PWM modulator 10 shown in FIG. 2. So, the PWM modulator 10 effectspulse-width modulation on the input signal Vin to produce a pulse-widthmodulated signal Vm shown in FIG. 3B. Herein, a duty ratio of thepulse-width modulated signal Vm changes in response to a voltage valueof the input signal Vin. That is, high-level durations of thepulse-width modulated signal Vm decrease as the voltage value decreases,while they increase as the voltage value increases. Therefore, the dutyratio of the pulse-width modulated signal Vm is adjusted by adjustingthe modulation factor, so that it is possible to obtain desiredinput/output characteristics with respect to the PWM modulator 10.

[0067] The PWM modulator 10 outputs an inverted signal Vm′, which is aninverse of the pulse-width modulated signal Vm. Such an inverted signalVm′ is supplied to the demodulator 20. In the demodulator 20, the secondlow-pass filter produces a demodulated signal V′, shown in FIG. 3D,based on the inverted signal Vm′. The demodulated signal V′ is suppliedto the amplitude detector 30. Herein, the diode D1 and the capacitor C6hold a negative peak voltage value Vb of the demodulated signal V′,while the diode D2 and the capacitor C5 hold a positive peak voltagevalue Va of the demodulated signal V′. Then, the operational amplifier31 calculates an amplitude value (Va−Vb) of the demodulated signal V′,which is inverted by the operational amplifier 32. Thereafter, outputsof the operational amplifiers 31, 32 are supplied to the PWM modulator10 as control signals (or control signal) Cs. Incidentally, it ispossible to set a gain by adequately setting a ratio between resistancesof the resistors R11, R10 and a ratio between resistances of theresistors R13, R12.

[0068] The PWM modulator 10 adjusts the modulation factor thereof inresponse to the control signal Cs. Concretely speaking, the outputs ofthe operational amplifiers 31 and 32 are respectively used as the sourcevoltages vh and vl of the buffer 13, so that it is possible to adjust afeedback value of the buffer 13. FIG. 3C shows a waveform of an outputof the buffer 13 whose feedback value is adjusted.

[0069] As for adjustment of the modulation factor, if the demodulatedsignal V′ has a large amplitude, the source voltages vh and vl becomecorrespondingly large. As a result, the feedback value increases, sothat the modulation factor decreases. On the other hand, if thedemodulated signal V′ has a small amplitude, the source voltages vh andvl become correspondingly small. Therefore, the feedback valuedecreases, so that the modulation factor increases.

[0070] Decrease of the modulation factor results in decrease of avariation rate of the duty ratio of the pulse-width modulated signal Vmagainst amplitude variations of the input signal Vin. On the other hand,increase of the modulation factor results in increase of the variationrate of the duty ratio of the pulse-width modulated signal Vm againstthe amplitude variations of the input signal Vin.

[0071] In short, it is possible to adjust a gain of the output signalVout against the input signal Vin by adjusting the modulation factor.Herein, the modulation factor is adjusted in response to the amplitudeof the demodulated signal V′, which may correspond to the output signalVout. Therefore, an overall input/output gain is adjusted in response tothe amplitude of the output signal Vout. In the present embodiment, theinput/output gain decreases as the amplitude of the output signal Voutincreases, while the input/output gain increases as the amplitude of theoutput signal Vout decreases. As a result, the amplitude compressiondevice of the present embodiment is capable of compressing a dynamicrange. FIG. 4 is a graph showing a curve which represents an example ofinput/output characteristics of the amplitude compression device.

[0072] As described above, the amplitude compression device of theembodiment 1 operates as follows:

[0073] The pulse-width modulation is effected on the input signal Vin,wherein the modulation factor is controlled in response to the amplitudeof the output signal Vout. The pulse-width modulated signal Vm isdemodulated to produce the output signal Vout.

[0074] According to the embodiment 1, it is possible to obtain“non-linear” input/output characteristics without using the logarithmiccharacteristics of the bipolar transistors. In addition, adjustment ofthe modulation factor is performed by adjusting the source voltages vh,vl of the buffer 13, which feeds back the “two-valued” pulse-widthmodulated signal Vm. So, the amplitude compression device can bemanufactured as an IC in accordance with the CMOS process with ease.

[0075] In addition, the present embodiment is capable of continuouslyvarying the gain thereof. Therefore, it is possible to obtain the“smooth” output signal. The present embodiment does not require digitaldata, which are produced for control. Thus, it is possible to obtain theoutput signal Vout having a high quality with a simple configuration ofcircuitry.

[0076] Further, the present embodiment is capable of directly processingthe “analog” input signal Vin without converting it to digital signal.Therefore, it is possible to manufacture the amplitude compressiondevice without using an A/D converter, a D/A converter and/or a DSP,which are expensive.

[0077] Furthermore, the amplitude compression device of the presentembodiment is designed to adjust the input/output gain by feeding backthe amplitude of the output signal Vout. Therefore, it is possible toobtain non-linear characteristics with good linearity.

[0078] [B] Embodiment 2

[0079] Next, a description will be given with respect to a configurationof an amplitude compression device in accordance with embodiment 2 ofthe invention.

[0080]FIG. 5 is a block diagram showing the amplitude compression deviceof the embodiment 2. Like the aforementioned embodiment 1 shown in FIG.1, the amplitude compression device of the embodiment 2 is configured bythe PWM modulator 10, the demodulator 20 and the amplitude detector 30.However, different from the embodiment 1 in which the output signal Voutis detected to produce the control signal Cs, the embodiment 2 isdesigned such that the amplitude detector 30 detects the amplitude ofthe input signal Vin to produce the control signal Cs. In other words,the embodiment 1 is configured in a feedback form, while the embodiment2 is configured in a feed-forward form.

[0081]FIG. 6 is a circuit diagram showing internal circuitconfigurations of the amplitude compression device of the embodiment 2,wherein parts equivalent to those shown in FIG. 2 are designated by thesame reference symbols.

[0082] Next, a description will be given with respect to operations ofthe amplitude compression device of the embodiment 2 with reference toFIG. 6.

[0083] In FIG. 6, an input signal Vin is supplied to the amplitudedetector 30. In the amplitude detector 30, a positive peak voltage valueof the input signal Vin is detected by the diode D2 and the capacitorC5, while a negative peak voltage value is detected by the diode D1 andthe capacitor C6. Then, the operational amplifier (or comparator) 31calculates an amplitude value of the input signal Vin, which is theninverted by the operational amplifier (or comparator) 32. Outputs of thecomparators 31 and 32 are supplied the PWM modulator 10 as controlsignals (or control signal) Cs. Herein, the control signal Cs representsthe amplitude value of the input signal Vin.

[0084] The input signal Vin is also supplied to the PWM modulator 10.So, the PWM modulator 10 effects pulse-width modulation on the inputsignal Vin to produce a pulse-width modulated signal Vm. Herein, a dutyratio of the pulse-width modulated signal Vm changes in response to avoltage value of the input signal Vin. In addition, a modulation factorof the pulse-width modulation is adjusted by a feedback value of thepulse-width modulated signal Vm, which is fed back to the invertinginput of the operational amplifier 11 by the buffer 13. Like theforegoing embodiment 1 shown in FIG. 2, the “two-valued” pulse-widthmodulated signal Vm having high and low levels is supplied to an inputof the buffer 13. As for the buffer 13, the positive source voltage vhand negative source voltage vl are respectively adjusted by the controlsignals Cs. Thus, the modulation factor is adjusted by the controlsignal Cs.

[0085] As described above, the control signal Cs corresponds to theamplitude value of the input signal Vin. Therefore, the modulationfactor is adjusted in response to the amplitude value of the inputsignal Vin. If the amplitude value of the input signal Vin becomeslarge, the source voltages vh and vl increase so that the feedback valueincreases, therefore, the modulation factor decreases. Decrease of themodulation factor results in decreases of a variation rate of the dutyratio of the pulse-width modulated signal Vm against amplitudevariations of the input signal Vin. As a result, an overall input/outputgain of the amplitude compression device decreases. In contrast, if theamplitude value of the input signal Vin becomes small, the sourcevoltages vh and vl decrease so that the feedback value decreases,therefore, the modulation factor increases. Increase of the modulationfactor results in increase of the variation rate of the duty ratio ofthe pulse-width modulated signal Vm against the amplitude variations ofthe input signal Vin. Thus, the input/output gain increases.

[0086] As described above, the amplitude compression device of theembodiment 2 as a whole operates to compress the dynamic range. Like theforegoing embodiment 1, the amplitude compression device of theembodiment 2 has input/output characteristics, which is shown by thecurve shown in FIG. 4.

[0087] In short, the embodiment 2 operates as follows:

[0088] The pulse-width modulation is effected on the input signal Vin.The modulation factor is controlled by the amplitude value of the inputsignal Vin, while the pulse-width modulated signal Vm is demodulated toproduce the output signal Vout.

[0089] Like the foregoing embodiment 1, the embodiment 2 provides theamplitude compression device, which can be manufactured in a form of anIC in accordance with the CMOS process with ease. In addition, theembodiment 2 is capable of continuously varying the gain. Further, theembodiment 2 is capable of processing the “analog” input signal withoutconverting it to digital signal. So, it is possible to configure theamplitude compression device without using the “expensive” circuitcomponents such as the A/D converter, D/A converter and/or DSP.

[0090] Next, modifications for the embodiments 1, 2 will be described asfollows:

[0091] (1) The embodiment 1 describes the amplitude compression deviceto have properties in which the input/output gain is increased while theamplitude of the output signal Vout is small, but the input/output gainis decreased while the amplitude of the output signal Vout is large.However, this invention is not limited to such embodiment 1. In otherwords, it is possible to change the properties of the amplitudecompression device. That is, the input/output gain is increased whilethe amplitude of the output signal Vout is large, but the input/outputgain is decreased while the amplitude of the output signal Vout issmall. Concretely speaking, the amplitude compression device of theembodiment 1 is modified such that the amplitude detector 30 decreasesthe control signal Cs as the detected amplitude of the output signalVout increases. In this case, when the amplitude of the output signalVout increases, the source voltages vh, vl of the buffer 13 decrease sothat the feedback value of the pulse-width modulated signal Vmdecreases, therefore, the modulation factor increases. Therefore, it ispossible to increase the input/output gain as the amplitude of theoutput signal Vout becomes large. In short, the embodiment 1 providesany types of the amplitude compression devices which are capable ofadjusting the amplitude of the input signal Vin by adjusting themodulation factor of the pulse-width modulation, which is effected onthe input signal Vin, based on the amplitude of the output signal Vout.

[0092] (2) The embodiment 2 describes the amplitude compression deviceto have properties in which the input/output gain is increased while theamplitude of the input signal Vin is small, but the input/output gain isdecreased while the amplitude of the input signal Vin is large. Thisinvention is not limited to such embodiment 2. In other words, it ispossible to change the properties of the amplitude compression device.That is, the input/output gain is increased while the amplitude of theinput signal Vin is large, but the input/output gain is decreased whilethe amplitude of the input signal Vin is small. Concretely speaking, theamplitude compression device of the embodiment 2 is modified such thatthe amplitude detector 30 decreases the control signal Cs as theamplitude of the detected input signal Vin increases. In this case, whenthe amplitude of the input signal Vin increases, the source voltages vh,vl of the buffer 13 decrease so that the feedback value of thepulse-width modulated signal Vm decreases, therefore, the modulationfactor increases. Therefore, it is possible to increase the input/outputgain as the amplitude of the input signal Vin becomes large. In short,the embodiment 2 provides any types of the amplitude compression deviceswhich are capable of effecting the pulse-width modulation having themodulation factor following the amplitude of the input signal Vin on theinput signal Vin and which is capable of demodulating the pulse-widthmodulated signal Vm to produce the output signal Vout.

[0093] (3) Both of the embodiments 1 and 2 are designed in such a mannerthat the amplitude detector 30 detects the amplitude by detecting thepositive and negative peak voltage values with respect to thedemodulated signal V′ (corresponding to the output signal Vout) or theinput signal Vin. However, this invention is not limited in such amanner. That is, it is possible to detect the amplitude by detectingeither the positive peak voltage value or negative peak voltage value.

[0094] [C] Embodiment 3

[0095] Next, a description will be given with respect to a full-waverectifier in accordance with embodiment 3 of the invention.

[0096]FIG. 7 is a circuit diagram showing a circuit configuration of afull-wave rectifier 500, which is mainly configured by an inversionamplifier 510, an amplifier 520 and an output section 530. Herein, theoutput section 530 is shared by the amplifiers 510 and 520.

[0097] The inversion amplifier 510 is configured by a constant currentsource 511, a pair of p-channel field-effect transistors P1, P2, a pairof n-channel field-effect transistors N1, N2 and resistors 512, 513 aswell as the output section 530. Herein, the field-effect transistors (orFETs) N1, N2 act as negative loads. In the inversion amplifier 510, agate of the p-channel FET P1 acts as an inverting input. An input signalVin applied to an input terminal IN is supplied to such an invertinginput of the inversion amplifier 510 via a resistor 512. In addition, anoutput signal Vout to be output from an output terminal OUT is fed backto the inverting input of the inversion amplifier 510 via a resistor513. Reference voltage Vr is applied to a gate of the p-channel FET P2.Both of the resistors 512 and 513 have same resistance “r”. Imaginaryshort-circuit is established between the gates of the p-channel FETs P1and P2. So, the inversion amplifier 510 has a gain of“−1”.

[0098] The amplifier 520 is configured by a constant current source 521,a pair of p-channel FETs P3, P4 and a pair of n-channel FETs N3, N4,which work as negative loads, as well as the output section 530. In theamplifier 520, a gate of the p-channel FET P4 acts as an invertinginput. The output signal Vout is fed back to such an inverting input ofthe amplifier 520. As for the amplifier 520, the output signal Vout isfully subjected to negative feedback. So, the amplifier 520 functions asa voltage follower, whose gain is “1”.

[0099] The output section 530 is configured by a constant current source531 and a pair of n-channel FETs N5, N6. Herein, drains of the n-channelFETs N5, N6 are connected together to form a connection terminal, fromwhich the output signal Vout is extracted. In addition, the drains ofthe n-channel FETs N5, N6 are connected to the gate of the p-channel FETP1 via the resistor 513. Further, a load resistor (not shown) isconnected to the output terminal OUT. Incidentally, the constant currentsource 531 supplies a very small amount of current.

[0100] Gates of the n-channel FETs N5, N6 serve as control terminals.Herein, an output signal of the inversion amplifier 510 is supplied tothe gate of the n-channel FET N5 which has gate voltage VG1, while anoutput signal of the amplifier 520 is supplied to the gate of then-channel FET N6 which has gate voltage VG2. The n-channel FET N5absorbs a current in response to the gate voltage VG1, while then-channel FET N6 absorbs a current in response to the gate voltage VG2.By the way, the output signals of the amplifiers 510 and 520 differ fromeach other in phases by 180°. Normally, a first FET corresponding to oneof the n-channel FETs N5 and N6 absorbs a current such as to reduce theoutput signal Vout in voltage to be lower than the reference voltage Vr.In this case, a second FET corresponding to another one of the FETs N5and N6 operates to increase the output signal Vout. For this reason, thesecond FET is reduced in gate voltage, however, the output signal Voutis not increased in voltage because the first FET absorbs the current.Thus, the gate voltage of the second FET becomes identical to groundlevel, so the second FET is in an OFF state.

[0101] As a result, the output section 530 selects one of the outputsignals of the amplifiers 510 and 520, which is lower than the referencevoltage Vr. So, the output section 530 outputs the selected signal asthe output signal Vout. Thus, the current is absorbed by either then-channel FET N5 or the n-channel FET N6 by means of the load resistor,so that the full-wave rectifier outputs the “negative” output signalVout.

[0102] According to the embodiment 3 described above, it is possible toconfigure the full-wave rectifier 500 by using only the FETs. Therefore,it is possible to manufacture the full-wave rectifier in accordance withthe MOS process with ease. Herein, the full-wave rectifier does notrequire diodes which are externally connected.

[0103] Next, a description will be given with respect to operations ofthe full-wave rectifier 500 with reference to time charts of FIGS. 8A to8D. Suppose that the input signal Vin shown in FIG. 8A is applied to theamplifiers 510 and 520 respectively. In a duration T1, the input signalVin is higher than the reference voltage Vr. The gate voltage VG1 of then-channel FET N5 has the same phase of the input signal Vin. So, thegate voltage VG1 has a waveform of FIG. 8B in the duration T1. In thiscase, the n-channel FET N5 absorbs a current in response to the gatevoltage VG1.

[0104] In the duration T1, the amplifier 520 operates to output a signalhaving a same phase of the input signal Vin. Therefore, the gate voltageVG2 decreases so that the n-channel FET N6 will not absorb the current.However, the n-channel FET N5 absorbs the current, so the voltage of theoutput signal Vout becomes lower than the reference voltage Vr. Thus,the gate voltage VG2 becomes identical to the ground level as shown inFIG. 8C, so that the n-channel FET N6 is in an OFF state. As a result,the output section 530 selects the output signal of the inversionamplifier 510, which is output as the output signal Vout in the durationT1. In the duration T1, the output signal Vout shown in FIG. 8D isequivalent to an inversion of the input signal Vin.

[0105] In a duration T2 in which the input signal is lower than thereference voltage Vr, the gate voltage VG2 applied to the gate of then-channel FET N6 increases as shown in FIG. 8C. So, the drain of then-channel FET N6 absorbs a current in response to the gate voltage VG2.This reduces the output signal Vout in voltage. In the inversionamplifier 510, the negative feedback is effected such that gate voltageof the p-channel FET P1 is identical to gate voltage of the p-channelFET P2. This increases drain voltage of the n-channel FET N5. Thus, then-channel FET N5 is controlled such that the current being absorbeddecreases. Therefore, the gate voltage VG1 of the n-channel FET N5decreases. In this case, however, the n-channel FET N6 is in an ONstate. So, even if the gate voltage VG1 of the n-channel FET N5 isreduced, the output signal Vout is not increased in voltage.

[0106] In the duration T2 described above, the amplifier 520 operates,while the inversion amplifier 510 stops operating. As a result, theoutput signal Vout shown in FIG. 8D has a same phase of the input signalVin in the duration T2.

[0107] The full-wave rectifier of the present embodiment is designedsuch that the output section 530 is configured using the n-channel FETsN5, N6, each of which operates to absorb the current. As a result, theoutput section 530 selects one of the output signals of the amplifiers510 and 520, which is lower than the reference voltage Vr. Thus, it ispossible to produce the output signal Vout which is subjected tofull-wave rectification. According to the present embodiment, all of theinversion amplifier 510, amplifier 520 and output section 530 of thefull-wave rectifier 500 are configured using the FETs without usingdiodes. Thus, it is possible to manufacture the full-wave rectifier 500in a form of an IC in accordance with the MOS process with ease.

[0108] [D] Embodiment 4

[0109] The aforementioned full-wave rectifier 500 of the embodiment 3 isdesigned to produce the “negative” output signal Vout. In contrast, afull-wave rectifier 600 of the embodiment 4 is designed to produce a“positive” output signal Vout.

[0110]FIG. 9 is a circuit diagram showing circuit configurations of thefull-wave rectifier 600 in accordance with the embodiment 4, whereinparts equivalent to those of FIG. 7 are designated by the same referencesymbols.

[0111] The full-wave rectifier 600 of FIG. 9 is mainly configured by aninversion amplifier 610, an amplifier 620 and an output section 630,which are basically equivalent to the inversion amplifier 510, theamplifier 520 and the output section 530 shown in FIG. 7.

[0112] The inversion amplifier 610 is configured by a constant currentsource 612, a pair of n-channel FETs N11, N12, a pair of p-channel FETsP11, P12 which act as active loads, and resistors 612, 613 as well asthe output section 630. In the inversion amplifier 610, a gate of then-channel FET N11 acts as an inverting input. An input signal Vin isapplied to such an inverting input of the inversion amplifier 610 viathe resistor 612. In addition, an output signal Vout is fed back to theinverting input of the inversion amplifier 610 via the resistor 613.Reference voltage Vr is applied to a gate of the n-channel FET N12.Herein, imaginary short-circuit is established between the gates of then-channel FETs N11, N12. So, the inversion amplifier 610 has a gain of“−1”.

[0113] The amplifier 620 is configured by a constant current source 622,a pair of n-channel FETs N13, N14 and a pair of p-channel FETs P13, P14which act as active loads as well as the output section 630. Like theforegoing amplifier 520 shown in FIG. 7, the amplifier 620 shown in FIG.9 functions as a voltage follower, which has a gain of “1”.

[0114] The output section 630 is configured by a constant current source632 and a pair of p-channel FETs P15, P16, drains of which are connectedtogether to form a connection terminal. The constant current source 632is connected to such a connection terminal corresponding to the drainsof the p-channel FETs P15, P16. Thus, the output signal Vout isextracted from the drains of the p-channel FETs P15, P16. In addition,the drains of the p-channel FETs P15, P16 are connected to the gate ofthe n-channel FET N11 via the resistor 613. Further, a load resistor(not shown) is connected to an output terminal OUT. Incidentally, theconstant current source supplies a very small amount of current.

[0115] Gates of the p-channel FETs P15, P16 serve as control terminals.An output signal of the inversion amplifier 610 is supplied to the gateof the p-channel FET P15, while an output signal of the amplifier 620 issupplied to the gate of the p-channel FET P16. In the aforementionedembodiment 3 shown in FIG. 7, the n-channel FETs N5, N6 absorb currentsin response to the gate voltages VG1, VG2 respectively. In contrast tothe embodiment 3, the embodiment 4 is designed such that currents flowfrom the p-channel FETs P15, P16 in response to their gate voltagesVG11, VG12 respectively.

[0116] Imaginary short-circuit is established between gates of then-channel FETs N11, N12. Using an amount of current “i” which flowstoward the input terminal IN, the output signal Vout is given by anequation (1), as follows:

Vout=i·r+Vr   (1)

[0117] Herein, i is given by an equation (2) as follows:

i=(Vr−Vin)/r   (2)

[0118] Thus, Vout is given by an equation (3) as follows:

Vout=2Vr−Vin   (3)

[0119] Therefore, Vout is greater than Vr by an amount of voltage bywhich Vin is lower than Vr.

[0120] By the way, the output signals of the amplifiers 610, 620 differfrom each other in phases by 180°. Normally, a first FET correspondingto one of the p-channel FETs P15, P16 makes the current to flow in sucha way that the voltage of the output signal Vout becomes greater thanthe reference voltage Vr. In this case, a second FET corresponding toanother one of the p-channel FETs P15, P16 operates to reduce the outputsignal Vout in voltage. For this reason, the gate voltage is increasedbut the first FET outputs the current, so the output signal Vout willnot be reduced in voltage. Thus, the gate voltage of the second FETbecomes identical to source voltage Vcc, so that the second FET is in anOFF state.

[0121] Namely, the output section 630 selects one of the output signalsof the amplifiers 610, 620, which is higher than the reference voltageVr. Thus, it is possible to obtain the output signal Vout, having thesame phase of the input signal Vin, which is subjected to full-waverectification.

[0122] According to the present embodiment described above, it ispossible to configure the full-wave rectifier 600 by using only theFETs. So, it is possible to manufacture the full-wave rectifier in aform of an IC in accordance with the MOS process with ease, wherein thefull-wave rectifier does not require diodes which are externallyconnected.

[0123] Next, a description will be given with respect to operations ofthe full-wave rectifier 600 of the embodiment 4 with reference to timecharts of FIGS. 10A to 10D. An input signal Vin shown in FIG. 10A isapplied to the amplifiers 610 and 620 respectively. In a duration T11,voltage of the input signal Vin is greater than the reference voltageVr. Gate voltage VG12 of the p-channel FET P16 has a reverse phase ascompared with the input signal Vin. In the duration T11, the gatevoltage VG12 varies as shown in FIG. 10C. In this case, the p-channelFET P16 makes a current to flow in response to the gate voltage VG12.

[0124] The inversion amplifier 610 operates to output a signal whosephase is reverse to the phase of the input signal Vin. Therefore, gatevoltage VG11 of the p-channel FET P15 increases, so that an amount ofcurrent that flows from the p-channel FET P15 decreases. However, acurrent flows from the p-channel FET P16, so that the voltage of theoutput signal Vout will not become lower than the reference voltage Vr.For this reason, the gate voltage VG11 becomes identical to the sourcevoltage Vcc as shown in FIG. 10B, so that the p-channel FET P15 is in anOFF state. In the duration T11, the output section 630 selects theoutput signal of the amplifier 620, which is output as the output signalVout. As shown in FIG. 10D, the output signal Vout has the same phase ofthe input signal Vin in the duration T11.

[0125] In a duration T12, the voltage of the input signal Vin becomeslower than the reference voltage Vr. So, the gate voltage VG11 of thep-channel FET P15 varies in the duration T12 as shown in FIG. 10B.Therefore, a current flows from the drain of the p-channel FET P15 inresponse to the gate voltage VG11. This increases the output signal Voutin voltage. In the amplifier 620, negative feedback is effected in sucha way that gate voltage of the n-channel FET N13 is identical to gatevoltage of the n-channel FET N14. As a result, the p-channel FET P16 iscontrolled such that the current flowing from the p-channel FET P16 isreduced. However, the p-channel FET P15 is in an ON state. Therefore,even if the gate voltage VG12 increases (see FIG. 10C), the outputsingal Vout is not reduced in voltage.

[0126] In the duration T12, the inversion amplifier 610 operates whilethe amplifier 620 stops operating. As shown in FIG. 10D, the outputsignal Vout has a reverse phase as compared with the input signal Vin inthe duration T12.

[0127] According to the present embodiment described above, the outputsection 630 is configured using the p-channel FETs P15 and P16, each ofwhich operates such that the current flows therefrom. As a result, theoutput section 630 selects one of the output signals of the amplifiers610 and 620, which is greater than the reference voltage Vr. Thus, it ispossible to obtain the output signal Vout which is subjected tofull-wave rectification. In the embodiment 4, all of the inversionamplifier 610, amplifier 620 and output section 630 of the full-waverectifier 600 are configured by the FETs without using the diodes. So,it is possible to manufacture the full-wave rectifier 600 in a form ofan IC in accordance with the MOS process with ease.

[0128] Incidentally, the output section 530 of the embodiment 3 isconfigured by the constant current source 531 and the n-channel FETs N5,N6, while the output section 630 of the embodiment 4 is configured bythe constant current source 632 and the p-channel FETs P15, P16.However, those output sections 530 and 630 are equivalent to each otherin operations. Because, the output section 530 selects and outputs oneof the output signals of the amplifiers 510 and 520, while the outputsection 630 selects and outputs one of the output signals of theamplifiers 610 and 620. That is, this invention is not limited to thoseembodiments. In other words, this invention provides any types of thefull-wave rectifiers, each of which has a function to adequately selectone of the output signals of the amplifiers.

[0129] Lastly, the aforementioned embodiments are designed to use theFETs as active components, for example. However, it is possible to usep-n-p bipolar transistors instead of the p-channel FETs, and it ispossible to use n-p-n bipolar transistors instead of the n-channel FETs.

[0130] As this invention may be embodied in several forms withoutdeparting from the spirit of essential characteristics thereof, thepresent embodiments are therefore illustrative and not restrictive,since the scope of the invention is defined by the appended claimsrather than by the description preceding them, and all changes that fallwithin metes and bounds of the claims, or equivalence of such metes andbounds are therefore intended to be embraced by the claims.

What is claimed is:
 1. A full-wave rectifier which produces a full-wave rectified signal by effecting full-wave rectification on an input signal, comprising: an amplifier for producing a first output signal whose phase is identical to a phase of the input signal; an inversion amplifier for producing a second output signal whose phase is reverse to the phase of the input signal; and an output section for switching over the first output signal and the second output signal to output the full-wave rectified signal.
 2. A full-wave rectifier according to claim 1 wherein each of the amplifier and inversion amplifier is configured using field-effect transistors and is of a feedback type to feed back the full-wave rectified signal thereto, and wherein the output section is equipped with a constant current source for supplying a constant current, a first field-effect transistor whose connection terminal is connected to the constant current source and whose control terminal receives the first output signal of the amplifier, and a second field-effect transistor whose connection terminal is connected to the constant current source and whose control terminal receives the second output signal of the inversion amplifier, so that the full-wave rectified signal is extracted from the connection terminals of the first and second field-effect transistors.
 3. A full-wave rectifier comprising: an inversion amplifier having a first inverting input to which an input signal is applied and to which an output signal corresponding to a full-wave rectified signal is fed back, the inversion amplifier amplifying the input signal with a gain of “−1” to produce a first output signal whose level is increased relatively high only in a first half duration of one period of the input signal; an amplifier having a second inverting input to which the output signal is fed back, the amplifier amplifying the input signal with a gain of “1” to produce a second output signal whose level is increased relatively high only in a second half duration of one period of the input signal; and an output section for producing a first portion of the full-wave rectified signal based on the first output signal of the inversion amplifier in the first half duration and for producing a second portion of the full-wave rectified signal based on the second output signal of the amplifier in the second half duration, wherein the first portion and the second portion are combined together to form a negative waveform for the full-wave rectified signal in response to one period of the input signal.
 4. A full-wave rectifier according to claim 3 wherein the inversion amplifier is configured using a first field-effect transistor whose gate corresponds to the first inverting input and a second field-effect transistor whose drain provides the first output signal.
 5. A full-wave rectifier according to claim 4 wherein the amplifier is configured using a third field-effect transistor whose gate receives the input signal and whose drain provides the second output signal, and a fourth field-effect transistor whose gate corresponds to the second inverting input.
 6. A full-wave rectifier according to claim 5 wherein the output section is configured using a pair of field-effect transistors whose drains are connected together to provide the output signal and whose gates receive the first and second output signals respectively
 7. A full-wave rectifier comprising: an amplifier having a first inverting input to which an output signal corresponding to a full-wave rectified signal is fed back, the amplifier amplifying the input signal with a gain of “1” to produce a first output signal whose level is reduced relatively low only in a first half duration of one period of the input signal; an inversion amplifier having a second inverting input to which an input signal is applied and to which the output signal is fed back, the inversion amplifier amplifying the input signal with a gain of “−1” to produce a second output signal whose level is reduced relatively low only in a second half duration of one period of the input signal; an output section for producing a first portion of the full-wave rectified signal based on the first output signal of the amplifier in the first half duration and for producing a second portion of the full-wave rectified signal based on the second output signal of the inversion amplifier in the second half duration, wherein the first portion and the second portion are combined together to form a positive waveform for the full-wave rectified signal in response to one period of the input signal.
 8. A full-wave rectifier according to claim 7 wherein the inversion amplifier is configured using a first d field-effect transistor whose gate corresponds to the second inverting input and a second field-effect transistor whose drain provides the second output signal.
 9. A full-wave rectifier according to claim 8 wherein the amplifier is configured using a third field-effect transistor whose gate receives the input signal and whose drain provides the first output signal, and a fourth field-effect transistor whose gate corresponds to the first inverting input.
 10. A full-wave rectifier according to claim 9 wherein the output section is configured using a pair of field-effect transistors whose drains are connected together to provide the output 